Data transmitting and receiving systems and methods are increasingly used to transmit increasing amounts of data at increasingly higher speeds. In data transmitting/receiving systems and methods, it may be desirable to encode (or code) the data to facilitate transmission and to later decode the encoded data that is received. One type of coding that is widely used is DC balance coding. As is well known to those having skill in the art, DC balance coding is a technique for coding data to provide enough state changes for reasonable clock recovery while achieving DC balance and bounded disparity among adjacent data symbols.
One widely used form of DC balance coding is referred to as “8B/10B coding”. As the scheme name suggests, in 8B/10B encoding, eight bits of data are transmitted as a 10-bit entity, often called a symbol or character. The least significant five bits of data are encoded into a 6-bit group, and the most significant three bits are encoded into a 4-bit group. These code groups are concatenated together to form the 10-bit symbol that is transmitted. Because 8B/10B encoding uses 10-bit symbols to encode 8-bit words, each of the 256 possible 8-bit words can be encoded in two different ways, one the bitwise inverse of the other. Using these alternative encodings, the scheme is able to effect long term DC balance. The 8B/10B encoding may be used in IEEE 1394b, Gigabit Ethernet, audio storage devices such as digital audio tape, and other widely used interfaces/devices.
8B/10B DC balance encoding is described in U.S. Pat. 4,486,739 to Franaszek et al., entitled “Byte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Code”. As stated in the Abstract of the Franaszek et al. patent, a binary DC balanced code and an encoder circuit for effecting same is described, which translates an eight bit byte of information into ten binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder is partitioned into a 5B/6B plus a 3B/4B coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.
Another example of 8B/10B encoding is described in U.S. Pat. No. 5,387,911 to Gleichert et al., entitled “Method and Apparatus for Transmitting and Receiving Both 8B/10B Code and 10B/12B Code in a Switchable 8B/10B Transmitter and Receiver”. As stated in the Abstract of Gleichert et al., a method and apparatus are provided for using a modified 8B/10B system for transmitting 10-bit wide data packets in 12-bit code in which 5B/6B encoder/decoders separate the 10-bit wide data into two 5-bit nibbles. Unique special codes are provided which are not capable of aliasing with other 12-bit code words to provide reliable byte boundaries.
FIG. 1 is a reproduction of FIG. 1 of U.S. Pat. No. 5,387,911 to Gleichert et al. As stated in Gleichert et al., at the top of Column 6, FIG. 1 is a block diagram of a prior art 8B wide architecture of both an 8B/10B transmitter 1 and receiver 2. A latch 4 and encoder 5 of transmitter 1 are configured to accept only 8-bit wide raw data and the encoder 5 was configured to convert the 8-bit raw data into 10-bit parallel code, which is then converted to serial data in shifter 7 and sent over transmission link 8 to the receiver 2. The receiver is also constrained to 8-bit architecture after the decoding of the 10-bit code in decoder 11.
FIG. 2A is a circuit diagram of a conventional data transmitting/receiving system, also referred to as an interface system 10, which includes a transmitter unit 20 and a receiver unit 30. Data bits DQ1 . . . DQN are applied to drivers D1-DN, to drive a plurality of signal or transmission lines Line1-LineN. At the receiver unit 30, a plurality of input buffers A1-AN may include termination resistors R1-RN that may be connected to a power supply voltage VDD. A reference voltage may also be applied to the input buffers A1-AN. The reference voltage may be generated by one or more resistors that are tied between the power supply voltage VDD and a ground voltage VSS, or using other conventional techniques. Internal power supply voltages and ground voltages are designated in FIG. 2A by VDDQ and VSSQ, respectively.
As also shown in FIG. 2A, parasitic inductances L1-L4 may exist in the interface system 10. These and/or other parasitic inductances may create Simultaneous Switching Noise (SSN) by creating a current path, as shown by the dotted line labeled IDQ ‘0’ in FIG. 2A, when transmitting a logic level ZERO. Thus, as shown in FIG. 2A, the drivers D1-DN are inverters. When the data is ONE, there may be no parasitic current path created. However, when the data is ZERO, a current path IDQ ‘0’ is created through the transmission lines Line1-LineN. According to the data level, the total current consumption of the drivers may thereby vary, which can create SSN. The parasitic inductances L1-L4 cause the noise (jitter) and may reduce the voltage margin and/or time margin of the data signal. The noise may also degrade the data frequency and/or system performance. SSN may also be created in an interface 10′ of FIG. 2B when the terminating resistors R1-RN of the receiver unit 30′ are tied to ground (VSS), when the data is ONE, as shown by the dotted line IDQ ‘1’. Since the SSN may be caused by parasitic inductors, the SSN may also be referred to as L(di/dt) Noise.
DC balance coding can reduce the above-described SSN. In particular, as shown in FIG. 3A, a large current variation in VSSQ may be caused during data transmission of 8-bit parallel data that is not DC balance coded. For example, as shown in FIG. 3A, data words D1-D4 of data bits DQ1-DQ8 are serially transmitted in what may also be referred to as a read/write operation. As between any two adjacent words, the difference in data bits may be up to eight (a transition from all ZEROs to all ONEs, or vice versa), as shown by the current variations of 8IDQ in FIG. 3A. These current variations can create large SSN or L(di/dt) Noise as shown in FIG. 3A. It will be understood by those having skill in the art that, in FIG. 3A, the terminology XIDQ, where X=0 . . . 8, indicates the numbers of ZEROs or ONEs in the 8-bit word. Thus, 3IDQ indicates three ZEROs and five ONEs (or vice versa), and 8IDQ indicates eight ZEROs and no ONEs (or vice versa).
FIG. 3B illustrates DC balance coding using 8B/10B coding schemes, wherein the minimum number of ONEs in a given word is 4, and the maximum number of ONEs in a given word is 6. Thus, as shown in FIG. 3B, an 8B/10B DC balance coded word includes 10 bits, where the number of ONEs is 4, 5 or 6, and the corresponding number of ZEROs is 6, 5 or 4. By reducing the current variation between adjacent words of 8B/10B DC balance coded data, L(di/dt) noise or SSN may be reduced.
Accordingly, DC balance encoding, such as 8B/10B DC balance encoding, can reduce simultaneous switching noise that is caused by parasitic inductances, to thereby allow high speed transmission. Nonetheless, as transmission speeds continue to increase, it may be desirable to further reduce simultaneous switching noise, even when using DC balance coding systems and methods, such as 8B/10B DC balance coding systems and methods.